UVM Framework Generation

SystemVerilog has become the language-of-choice for functional verification because it is open-source and not proprietary. But SystemVerilog is an extremely large and complex language to learn and use.

 UVM itself is SystemVerilog and it is complex and challenging to learn and use. It consists of about 300 base classes. Even given the most comprehensive training classes, there is still a need for help to get started with the first project.

A UVM framework generator is a good means to streamline and speed-up the adoption of UVM in companies. It saves up to 6 weeks of development time, guarantees the same testbench structure for different projects helping to reduce the maintenance cost for UVM testbencges, provides a UVM compliant verification environment and project teams are encouraged and motivated to adopt UVM where otherwise they might give up in frustration because of running in basic pitfalls of SystemVerilog and UVM.

The UVM framework generator developed by me needs as input the functional interfaces of the Design-Under-Test (DUT) and data to be processed by sequences. With this input data a complete UVM envrionment will be generated which is able to execute example sequences from example tests. It delivers also compilation and simulation scripts.

The common flow for the UVM framework generator is shown in the following figure.